Built In Self Test (BIST)

1. Definition: What is Built In Self Test (BIST)?

Built In Self Test (BIST) is a sophisticated testing methodology integrated into electronic systems, particularly within the realm of Digital Circuit Design, which enables devices to perform self-diagnostic tests autonomously. BIST is crucial for ensuring the reliability and functionality of semiconductor devices, especially in the context of Very Large Scale Integration (VLSI) systems. The primary role of BIST is to facilitate the detection and identification of faults during the manufacturing process and throughout the operational lifecycle of the device, thereby enhancing the overall quality assurance process.

The importance of BIST lies in its ability to reduce the dependency on external testing equipment and personnel, thereby minimizing testing costs and time. Traditional testing methods often involve complex setups and can be prone to human error; BIST addresses these shortcomings by embedding test capabilities directly within the hardware. This self-testing capability is particularly valuable in environments where devices are deployed in inaccessible locations or where downtime is costly, such as in aerospace, automotive, and telecommunications applications.

BIST employs various technical features, including built-in test pattern generators, response analyzers, and fault dictionaries, which work in concert to execute a series of diagnostic tests. These features allow for the generation of deterministic test patterns that can effectively stimulate the circuit under test (CUT) and analyze the resulting outputs against expected values. The self-contained nature of BIST not only enhances fault coverage but also supports ongoing maintenance and reliability assessments throughout the product’s lifecycle.

In summary, BIST is an essential component in modern semiconductor technology that streamlines the testing process, enhances fault detection capabilities, and ultimately contributes to the production of high-quality electronic devices.

2. Components and Operating Principles

The architecture of Built In Self Test (BIST) typically comprises several key components that work together to facilitate self-testing. These components include the Test Pattern Generator (TPG), the Circuit Under Test (CUT), the Response Analyzer (RA), and the Control Logic. Each of these elements plays a vital role in the BIST process, and their interactions are critical to the successful execution of the self-test.

2.1 Test Pattern Generator (TPG)

The Test Pattern Generator is responsible for creating deterministic test patterns that will stimulate the CUT. These patterns can be generated using various algorithms, including pseudo-random pattern generation, deterministic pattern generation, or a combination of both. The choice of pattern generation method is influenced by the specific requirements of the circuit being tested, including its complexity and the types of faults that are most likely to occur.

In many cases, the TPG is designed to produce a sequence of input vectors that can effectively exercise all functional paths within the CUT. This is particularly important in VLSI systems, where the sheer number of possible states can make exhaustive testing impractical. Advanced TPGs may also incorporate features such as compression techniques to reduce the amount of test data needed, thereby optimizing storage and transmission requirements.

2.2 Circuit Under Test (CUT)

The Circuit Under Test represents the actual hardware component being evaluated. It can be any digital circuit, such as an arithmetic logic unit (ALU), memory module, or a complete system-on-chip (SoC). The CUT is designed to respond to the input patterns generated by the TPG, and its outputs are monitored during the testing process.

The CUT must be designed with testability in mind, often requiring design-for-test (DFT) techniques to facilitate easier access to internal nodes and states. This allows for a more thorough evaluation of the circuit’s functionality and aids in the isolation of faults.

2.3 Response Analyzer (RA)

The Response Analyzer plays a critical role in the BIST process by comparing the actual outputs of the CUT against the expected outputs derived from the test patterns. This component can utilize various methods for analysis, including signature analysis, where a compact representation of the output is generated and compared to a known good signature.

The RA may also incorporate fault dictionaries that contain predefined signatures for various fault types. By analyzing the outputs against these signatures, the RA can effectively identify the presence of faults and classify them according to their nature.

2.4 Control Logic

Control Logic orchestrates the overall BIST process, managing the sequence of operations between the TPG, CUT, and RA. This component ensures that the test patterns are applied in a controlled manner and that the results are accurately recorded and analyzed. Control Logic can be implemented using finite state machines (FSMs) or other control structures, enabling flexibility in the testing process.

The interaction between these components is crucial for the successful implementation of BIST. The TPG generates patterns that are fed into the CUT, which processes the inputs and produces outputs. The RA then evaluates these outputs, and the Control Logic coordinates the entire operation, ensuring that the system functions as intended.

Built In Self Test (BIST) is often compared to other testing methodologies, such as Automatic Test Equipment (ATE) and boundary scan testing. Each of these approaches has its unique features, advantages, and disadvantages, which can influence their suitability for specific applications.

3.1 Automatic Test Equipment (ATE)

Automatic Test Equipment involves external devices that apply test patterns to a circuit and analyze the outputs. ATE systems are highly sophisticated and can provide extensive fault coverage, but they require physical access to the device under test and can incur significant costs associated with equipment and labor.

In contrast, BIST eliminates the need for external testing equipment, allowing devices to self-test without requiring human intervention. This can lead to reduced testing time and costs, especially in high-volume manufacturing scenarios. However, ATE may still outperform BIST in terms of fault coverage and accuracy for complex systems, making it a preferred choice for initial validation phases.

3.2 Boundary Scan Testing

Boundary scan testing, defined by the IEEE 1149.1 standard, is another technique that enables testing of digital circuits by providing access to internal nodes through special test access ports. This method is particularly useful for testing interconnections in multi-chip packages and can be complementary to BIST.

While boundary scan testing focuses on the connectivity and integrity of the interconnections, BIST is primarily concerned with the functional verification of the CUT itself. In many cases, both methodologies can be employed together to achieve comprehensive testing coverage. BIST can be used for internal functional testing, while boundary scan can provide insights into external connections and inter-chip communication.

3.3 Comparison Summary

In summary, while BIST offers significant advantages in terms of cost, efficiency, and ease of implementation, it may not always provide the exhaustive fault coverage that ATE systems can achieve. Boundary scan testing serves a different purpose but can complement BIST in enhancing overall test effectiveness. The choice between these methodologies depends on the specific requirements of the application, including factors such as device complexity, production volume, and testing budget.

4. References

IEEE Computer Society
International Test Conference (ITC)
Semiconductor Industry Association (SIA)
International Society for Test and Measurement (ISTM)
Various semiconductor manufacturers and testing equipment suppliers

5. One-line Summary

Built In Self Test (BIST) is an integrated testing methodology that enables electronic devices to autonomously perform self-diagnostic tests, enhancing reliability and reducing testing costs.