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10 November 2024

PBA vs GBA in Static Timing Analysis

Static Timing Analysis, STA์—์„œ Path Base Analysis, PBA์™€ Graph Base Analysis, GBA๋Š” ๋””์ง€ํ„ธ ํšŒ๋กœ์˜ ํƒ€์ด๋ฐ์„ ๋ถ„์„ํ•˜๋Š” ๋ฐ ์‚ฌ์šฉ๋˜๋Š” ๋‘ ๊ฐ€์ง€ ๋ฐฉ๋ฒ•์ž…๋‹ˆ๋‹ค.

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(1) ๊ฐ€์žฅ ์ •ํ™•ํ•˜๊ฒŒ ์‹ค๋ฆฌ์ฝ˜์˜ Timing Analysis๋ฅผ ํ•˜๋ ค๋ฉด, SPICE Level์—์„œ ์‹œ๋ฎฌ๋ ˆ์ด์…˜ ํ•˜๋Š” ๊ฒƒ์ž…๋‹ˆ๋‹ค.

(2) ๊ทธ๋Ÿฌ๋‚˜ SPICE Simulation์€ ๋„ˆ๋ฌด ๋ฌด๊ฒ๊ณ  ๋А๋ฆฝ๋‹ˆ๋‹ค. ๊ฒฐ๊ตญ SPICE Simulation์—์„œ GBA ๋ฐฉ์‹์˜ STA๋กœ ๋ฐœ์ „ํ•˜๊ฒŒ ๋˜์—ˆ์Šต๋‹ˆ๋‹ค.

(3) GBA๋Š” ๊ณ„์‚ฐ์ด ๋‹จ์ˆœํ•ฉ๋‹ˆ๋‹ค. ๋Œ€์‹ ์— ์ข€ ๋” ๋น„๊ด€์ ์ธ ๊ฒฐ๊ณผ๋ฅผ ๋ณด์ž…๋‹ˆ๋‹ค. ๊ทธ๋ž˜์„œ ๋Ÿฐํƒ€์ž„์ด ์ข€ ๋Š˜์–ด๋‚˜๋”๋ผ๋„, ์ข€ ๋” ์ •ํ™•ํ•œ ๋ฐฉ๋ฒ•๋ก ์ด ํ•„์š”ํ•ด์กŒ์Šต๋‹ˆ๋‹ค.

-> PBA๊ฐ€ ๋‚˜์™”์Šต๋‹ˆ๋‹ค.

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PBA, GBA ๋น„๊ตํ•˜๋Š” ๋…ผ๋ฌธ๋“ค์„ ๋ณด๋ฉด ์—ฌ๋Ÿฌ ๋””์ž์ธ์—์„œ Trade-off๋ฅผ ๋ณผ ์ˆ˜ ์žˆ์Šต๋‹ˆ๋‹ค.

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๊ฐ„๋‹จํžˆ ์š”์•ฝํ•˜๋ฉด,

GBA๋Š” ๊ณ„์‚ฐ์ด ๊ฐ„๋‹จ + ํ˜„์‹ค๋ณด๋‹ค ๋” ๋น„๊ด€์ ์ธ ๊ฒฐ๊ณผ ๊ฐ’(๊ฒฐ๊ณผ ๋งค์šฐ ๋‚˜์จ)

PBA๋Š” ๊ณ„์‚ฐ์ด ๋ณต์žก(Runtime ๊น€) + ํ˜„์‹ค์— ๊ฐ€๊นŒ์šด ๋œ ๋น„๊ด€์ ์ธ ๊ฒฐ๊ณผ ๊ฐ’

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์˜ˆ๋ฅผ๋“ค์–ด ์•„๋ž˜์™€ ๊ฐ™์€ 2-input NAND Gate๊ฐ€ ์žˆ๋‹ค๊ณ ํ•ฉ์‹œ๋‹ค.

0

Static Timing Analysis๋Š” ๊ธฐ๋ณธ์ปจ์…‰์œผ๋กœ๋Š” Single Input Switching์„ ๊ฐ€์ •ํ•ฉ๋‹ˆ๋‹ค.

(ํ˜„์‹ค ์„ธ๊ณ„์—์„œ๋Š” Multi Input Switching์ด ๋ฐœ์ƒํ•˜์ง€๋งŒ, ๊ธฐ๋ณธ STA๋Š” MIS๋ฅผ ๊ณ ๋ คํ•˜์ง€ ์•Š์Šต๋‹ˆ๋‹ค. ๊ด€๋ จ ๋‚ด์šฉ๋„ ์ดํ›„์— ๋‹ค๋ค„๋ณด๊ฒ ์Šต๋‹ˆ๋‹ค.)

  1. A to Y,

  2. B to Y,

2 ๊ฐœ์˜ Timing Arc๊ฐ€ ๊ธฐ๋ณธ์ž…๋‹ˆ๋‹ค.

๊ทธ๋ฆฌ๊ณ  A to Y, B to Y ๋ชจ๋‘ ๋‹ค๋ฅธ ๋ฌผ๋ฆฌ์  ํŠน์„ฑ์„ ๊ฐ–๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

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์˜ˆ๋ฅผ๋“ค์–ด Path ๋ณ„ Min delay Max delay๊ฐ€ ์•„๋ž˜์™€ ๊ฐ™๋‹ค๊ณ  ํ•ฉ์‹œ๋‹ค.
  1. A to Y, 1ns 10ns

  2. B to Y, 2ns 20ns

GBA๋Š” ์ด Cell์˜ Delay๊ฐ€ 1ns, 20ns์˜ ํŠน์„ฑ์„ ๊ฐ–๋Š”๋‹ค๊ณ  ํ•ฉ๋‹ˆ๋‹ค.

PBA๋Š” Swiching์ด

(1) A input์„ ํ†ตํ•˜๋Š” ๊ฒฝ์šฐ 1ns, 10ns ํŠน์„ฑ์„ ๊ฐ–๋„๋ก ํ•˜๊ณ ,

(2) B input์„ ํ†ตํ•˜๋Š” ๊ฒฝ์šฐ 2ns, 20ns ํŠน์„ฑ์„ ๊ฐ–๊ฒŒ ํ•ฉ๋‹ˆ๋‹ค.

1

์œ„ ๊ทธ๋ฆผ์—์„œ ์˜ˆ๋ฅผ ๋“ค๋ฉด,

input1 to Flipflop/D๊นŒ์ง€

GBA:

min: 3ns+1ns = 4ns

max: 4ns+20ns = 24ns

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PBA:

min: 3ns+1ns = 4ns

max: 4ns+10ns = 14ns

์ด๋Ÿฐ ๊ฒฝ์šฐ์—๋Š” maximum delay๊ฐ€ ์‹ค์ œ์ ์œผ๋กœ๋Š” 14ns๋งŒ ๋ฐœ์ƒํ•จ์—๋„, GBA๋Š” 24ns๋กœ ๋ณด๊ฒŒ๋ฉ๋‹ˆ๋‹ค.

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2

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GBA๋Š” Cell ์ „์ฒด Timing arc๋ฅผ ๋ณด๊ณ  min delay์™€ max delay๋ฅผ ๊ฐ–๊ณ , ์ด cell์„ ๊ฑฐ์น˜๋Š” ๊ฒฝ์šฐ ์ด ๊ฐ’์„ ์ ์šฉํ•˜๋„๋ก ํ•ฉ๋‹ˆ๋‹ค.

PBA๋Š” Signal์„ Activation์‹œํ‚ค๋Š” Path๋ฅผ ๊ธฐ๋ฐ˜์œผ๋กœ min delay์™€ max delay๋ฅผ ๊ฐ–๊ณ  Timing์„ ๋ถ„์„ํ•ฉ๋‹ˆ๋‹ค.

3-input NAND, AOI Gate ๊ฐ™์€ ๊ฒฝ์šฐ ๋งŽ์€ input pin์„ ๊ฐ–๊ณ , ๊ทธ ๋œป์€ ๋งŽ์€ Library Look up table์„ ๊ฐ–๋Š”๋‹ค๋Š” ๋œป์ž…๋‹ˆ๋‹ค. ๋ฐ์ดํ„ฐ๋ฅผ ๊ฐ–๊ณ  ์˜ฌ ๋•Œ ์ˆœํšŒํ•˜๋Š” ์‹œ๊ฐ„์ด ๊ธธ์–ด์ง‘๋‹ˆ๋‹ค.

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์ข€ ๋” ์ด๋ก ์ ์ธ ๋‚ด์šฉ์€ UC Sandiago์˜ Andrew Kahng ๊ต์ˆ˜๋‹˜์˜ ์ž๋ฃŒ๋ฅผ ์ฐธ๊ณ ํ•˜์‹œ์ฃ .

https://vlsicad.ucsd.edu/Publications/Conferences/361/c361.pptx

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Machine Learning PBA ์ด๋Ÿฐ๊ฒƒ๋“ค์€ ์œ„ GBA์™€ PBA ์‚ฌ์ด์—์„œ Runtime๊ณผ ๊ฒฐ๊ณผ๋ฅผ ์–ด๋А์ •๋„ Trade-off๋ฅผ ๋งž์ถ˜ ๋ฐฉ๋ฒ•๋ก ๋“ค์ด๋ผ๊ณ  ๋ณด์‹œ๋ฉด ๋ฉ๋‹ˆ๋‹ค.

https://ieeexplore.ieee.org/document/8615746

Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis : With diminishing margins in advanced technology nodes, accuracy of timing analysis is a serious concern. Improved accuracy helps to reduce overdesign, particularly in P&R-based optimization and timing closure steps, but comes at the cost of runtime. A major factor in accurate estimation of timing slโ€ฆ

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