Floorplanning

Definition: Floorplanning is a crucial early stage in the physical design of integrated circuits where the approximate location of major functional blocks is decided. It provides a high-level view of the chip’s layout, considering factors such as block sizes, interconnections, and overall chip dimensions.

Objectives:

  1. Minimize chip area
  2. Optimize interconnect length and performance
  3. Facilitate power distribution
  4. Enable efficient clock tree synthesis
  5. Manage thermal distribution

Key Concepts:

  1. Core Area:
    • Central region of the chip where functional blocks are placed
  2. I/O Pads:
    • Peripheral regions for connecting the chip to the outside world
  3. Aspect Ratio:
    • Ratio of chip’s width to height, often determined by package constraints
  4. Utilization:
    • Percentage of core area occupied by functional blocks
  5. Power Planning:
    • Initial definition of power grid structure

Floorplanning Process:

  1. Analyze design hierarchy and connectivity
  2. Estimate block sizes
  3. Define chip dimensions and I/O locations
  4. Place macro blocks and hard IP
  5. Define power grid structure
  6. Allocate space for standard cell placement
  7. Optimize and iterate

Types of Floorplanning:

  1. Slicing Floorplan:
    • Recursively partitions the chip area using horizontal and vertical cuts
  2. Non-Slicing Floorplan:
    • More flexible arrangement, often using algorithms like simulated annealing
  3. Hierarchical Floorplan:
    • Top-down approach for managing complexity in large designs

Example: Simple Floorplan Representation (ASCII Art)

+------------------------------+
|    +--------+    +--------+  |
|    |        |    |        |  |
|    |  CPU   |    |  DSP   |  |
|    |        |    |        |  |
|    +--------+    +--------+  |
|                              |
|    +--------+    +--------+  |
|    |        |    |        |  |
|    |  MEM   |    |  I/O   |  |
|    |        |    |        |  |
|    +--------+    +--------+  |
+------------------------------+

Advanced Floorplanning Concepts:

  1. Voltage Islands:
    • Regions operating at different supply voltages
  2. Mixed-Signal Floorplanning:
    • Segregating and shielding analog and digital components
  3. Thermal-Aware Floorplanning:
    • Distributing heat-generating blocks to manage thermal hotspots
  4. 3D IC Floorplanning:
    • Considering vertical stacking and through-silicon vias (TSVs)
  5. Chiplet-based Floorplanning:
    • Arranging multiple die within a package

Challenges in Floorplanning:

  1. Block Shapes:
    • Handling non-rectangular blocks and IP cores
  2. Congestion Management:
    • Predicting and mitigating routing congestion
  3. Timing Closure:
    • Ensuring floorplan supports timing requirements
  4. Power Integrity:
    • Ensuring robust power delivery across the chip

Floorplanning Tools:

  • Cadence Innovus
  • Synopsys IC Compiler
  • Mentor Calibre

Best Practices:

  1. Start floorplanning early in the design process
  2. Consider both top-down and bottom-up approaches
  3. Leave space for buffer insertion and ECO changes
  4. Pay attention to critical paths and timing requirements
  5. Iterate and refine based on downstream design stages feedback

Example: TCL Commands for Basic Floorplanning

# Define core area
create_floorplan -core_aspect_ratio 1 -core_utilization 0.7 -left_io2core 30 -bottom_io2core 30 -right_io2core 30 -top_io2core 30

# Place macro blocks
place_block {CPU} -fixed {100 100}
place_block {MEM} -fixed {500 100}

# Create power rings
create_power_rings -nets {VDD VSS} -layer {M1 M2} -width 5 -spacing 2

Future Trends in Floorplanning:

  1. AI/ML-driven floorplan optimization
  2. Integration with early-stage architectural exploration tools
  3. Enhanced support for heterogeneous integration and advanced packaging
  4. Automated floorplanning for complex SoCs
  5. Quantum computing-aware floorplanning methodologies

Floorplanning sets the foundation for successful chip design, influencing nearly every subsequent step in the physical design process. As chip complexities increase and new technologies emerge, effective floorplanning becomes ever more critical in achieving optimal performance, power, and area targets.